1. Field of the Invention
A method and device for avalanche testing of top and bottom FETs of a DC to DC buck converter.
2. Background Art
In the last few years it has become very critical to screen defective devices before the final assembly of a module in order to reduce cost.
Known Good Die (KGD) test systems using probes and/or pogo pin contacts are available to guarantee that only good dies will be assembled in the final module, although these systems can be expensive.
However, a critical test that is difficult to implement using a probe is the avalanche test. All semiconductor devices are rated for a certain maximum reverse voltage (BVdss for power MOSFETs). Operation above this threshold will cause high electric fields in reverse-biased p-n junctions. Due to impact ionization, these fields create electron-hole pairs that undergo a multiplication (avalanche) effect leading to increasing current. This reverse current flow causes large power dissipation and temperature rise, and potentially may cause the destruction of the device. However, the KGD system is capable of avalanche testing only up to 80 A of peak current for a 157 mils×50 mils die.
Due to the introduction of low cost packages it has quite often become convenient to go to production with the die not tested by the KGD system but tested for avalanche at final test, once the die are already in the package. Although convenient, this technique may lead to higher costs due to defective packages.
FIG. 1 shows the typical schematic of a module 100 including an IC 110 for a single-phase synchronous DC-DC buck converter such as a converter of the iP200x Series manufactured by International Rectifier Corp. and described in more detail at www.irf.com, incorporated by reference.
FIG. 2 shows the typical schematic including a module 200 and an IC 210 for a fully functional multi-phase synchronous DC-DC buck converter, such as a converter of the iP120x Series manufactured by International Rectifier Corp. and described in more detail at www.irf.com, incorporated by reference.
At final test it is possible to test the power loss of each single module built. A typical application circuit is implemented in the load board.
With a series of relays we are able to disconnect the input circuit, the output circuit and all the power supplies. The DRAIN and SOURCE for both the top and the bottom FETs are available for testing.
A decoupled VDD voltage source has been used for avalanche testing, as illustrated in FIGS. 9 and 10. Here a driver FET and recirculation diode are added so that the voltage drop across the inductor during avalanche is equal to the avalanche voltage. With this circuit the energy can be approximated as:
      E    AS    =            1      2        ⁢          L      ·              I        AS        2            
For further reference, FIGS. 11 and 12 depict ideal and actual avalanche waveforms, respectively. Note that the peak avalanche voltage VAV can be approximated as 1.3 times the device rating, or 650V. Further note that V(BR)DSS, BVdss and VAV are used interchangeably.
The following issues are presented by the buck converter of FIG. 1:    The GATEs of both top and bottom FETs Qt, Qb are not accessible for testing    The input cap Cin is part of the avalanche circuit    When we test avalanche on the bottom FET Qb, the SOURCE voltage of the top FET Qt rises up to BVdss and can damage the GATE of the top FET Qt which may be only 20V rated. Also, the IC 110 is not rated up to the BVdss of the bottom FET Qb.
Additional issues are presented by the buck converter of FIG. 2:    The IC input 210 is not rated up to BVdss of the top FET Qt.    The only way to shut down the bottom FET Qb and turn on the top FET Qt is to switch the IC 210.